Abort Free SemanticTM by Dependency Aware Scheduling of Transactional Instructions
نویسندگان
چکیده
We present a TM system that executes transactions without ever causing any aborts. The system uses a set of t-var lists, one for each transactional variable. A scheduler undertakes the task of placing the instructions of each transaction in the appropriate t-var lists based on which t-variable each of them accesses. A set of worker threads are responsible to execute these instructions. Because of the way instructions are inserted in and removed from the lists, by the way the worker threads work, and by the fact that the scheduler places all the instructions of a transaction in the appropriate tvar lists before doing so for the instructions of any subsequent transaction, it follows that no conflict will ever occur. Parallelism is fine-grained since it is achieved at the level of transactional instructions instead of transactions themselves (i.e., the instructions of a transaction may be executed concurrently).
منابع مشابه
Distributed Quantum Computing
In conjunction with DISC 2013, the TransForm project (Marie Curie Initial Training Network) and EuroTM (COST Action IC1001) supported the 5th edition of the Workshop on the Theory of Transactional Memory (WTTM 2013). The objective of WTTM was to discuss new theoretical challenges and recent achievements in the area of transactional computing with emphasis on transactional memory. The workshop t...
متن کاملNon-preemptive Scheduling of Real-Time Software Transactional Memory
Recent embedded processor architectures containing multiple heterogeneous cores and non-coherent caches, bring renewed attention to the use of Software Transactional Memory (STM) as a building block for developing parallel applications. STM promises to ease concurrent and parallel software development, but relies on the possibility of abort conflicting transactions to maintain data consistency,...
متن کاملDynamically Scheduling VLIW Instructions with Dependency Information
This paper proposes balancing scheduling effort more evenly between the compiler and the processor, by introducing dynamically scheduled Very Long Instruction Word (VLIW) instructions. Dynamically Instruction Scheduled VLIW (DISVLIW) processor is aimed specifically at dynamic scheduling VLIW instructions with dependency information. The DISVLIW processor dynamically schedules each instruction w...
متن کاملStarvation Freedom in Multi-Version Transactional Memory Systems
Software Transactional Memory systems (STMs) have garnered significant interest as an elegant alternative for addressing synchronization and concurrency issues with multi-threaded programming in multi-core systems. In order for STMs to be efficient, they must guarantee some progress properties. This work explores the notion of starvation-freedom in Software Transactional Memory Systems (STMs). ...
متن کاملContention-Aware Lock Scheduling for Transactional Databases
Lock managers are among the most studied components in concurrency control and transactional systems. However, one question seems to have been generally overlooked: “When there are multiple lock requests on the same object, which one(s) should be granted first?” Nearly all existing systems rely on a FIFO (first in, first out) strategy to decide which transaction(s) to grant the lock to. In this...
متن کامل